APPENDIX H
Details of the Z-80 and 8080 Instruction Set
A summary of the Z-80 and 8080 instruction set is given in this appendix.* The instructions are listed alphabetically by the official Zilog mnemonic. If there is a corresponding 8080 instruction, the Intel mnemonic is shown in angle brackets; if not, "no 8080" is shown in the angle brackets. The Z-80 mnemonics are listed in numeric order in Appendix F. The Z-80 equivalent of an 8080 mnemonic can be found from the cross-reference given in Appendix G.
The letters A, B, C, D, E, H, I, L, IX, IY, R, and SP are used for the standard Z-80 register names. In addition, the symbols BC, DE, and HL are used for the register pairs. The following symbols are used for general arguments.
r, r2 8-bit CPU register
rr 8-bit CPU register pair
dd 8-bit signed displacement
nn general 8-bit constant
nnnn 16-bit constant
The flag bits are represented by:
C carry
H half carry
N add/subtract
P/O parity/overflow
S sign
Z zero
Pointers to memory or input or output addresses are enclosed in parentheses.
* More details can be obtained from the Zilog programmer's manual, Z-80 Assembly Language Programming Manual, Zilog, Inc., 1977.
--------------------------------------------------
ADC A,(HL) [1/7] <ADC M> [1/7]
ADC A,(HL) $8E
Add the memory byte pointed to by the HL register pair to the accumulator and the carry flag. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag reset: N
--------------------------------------------------
ADC A,(IX+dd) [3/19] <no 8080>
ADC A,(IY+dd) [3/19] <no 8080>
ADC A,(IX+dd) $DD $8E dd
ADC A,(IY+dd) $FD $8E dd
Add the memory byte referenced by the sum of the specified index register and the displacement to the accumulator and the carry flag. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag reset: N
--------------------------------------------------
ADC A,r [1/4] <ADC r> [1/4]
ADC A,A $8F <ADC A>
ADC A,B $88 <ADC B>
ADC A,C $89 <ADC C>
ADC A,D $8A <ADC D>
ADC A,E $8B <ADC E>
ADC A,H $8C <ADC H>
ADC A,L $8D <ADC L>
Add the value in register r to the accumulator and the carry flag. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flags reset: N
--------------------------------------------------
ADC A,nn [2/7] <ACI nn> [2/7]
ADC A,nn $CE nn <ACI nn>
Add the constant given in the second operand to the accumulator and the carry flag. The result is placed in the accumulator.
Flags affected: C, H, 0, S, Z
Flag reset: N
--------------------------------------------------
ADC HL,rr [2/15] <no 8080>
ADC HL,BC $ED $4A
ADC HL,DE $ED $5A
ADC HL,HL $ED $6A
ADC HL,SP $ED $7A
Add the indicated double register to the HL register and the carry flag. The result is placed in HL.
Flags affected: C, H, O, S, Z,
Flag reset: N
--------------------------------------------------
ADD A,(HL) [1/7] <ADD M> [1/7]
ADD A,(HL) $86 <ADD M>
Add the memory byte pointed to by the HL pair to the accumulator. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag reset: N
--------------------------------------------------
ADD A,(IX+dd) [3/19] <no 8080>
ADD A,(IY+dd) [3/19] <no 8080>
ADD A,(IX+dd) $DD $86 dd
ADD A,(IY+dd) $FD $86 dd
Add the memory byte pointed to by the sum of the specified index register and the displacement to the accumulator. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag reset: N
--------------------------------------------------
ADD A,r [1/4] <ADD r> [1/4]
ADD A,A $87 <ADD A>
ADD A,B $80 <ADD B>
ADD A,C $81 <ADD C>
ADD A,D $82 <ADD D>
ADD A,E $83 <ADD E>
ADD A,H $84 <ADD H>
ADD A,L $85 <ADD L>
Add the value in register r to the accumulator. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag reset: N
--------------------------------------------------
ADD A,nn [2/7] <ADI nn> [2/7]
ADD A,nn $C6 nn <ADI nn>
Add the immediate byte (the second operand) to the accumulator. The result is placed in A.
Flags affected: C, H, O, S, Z
Flag reset: N
--------------------------------------------------
ADD HL,rr [1/11] <DAD B> [1/10]
ADD HL,BC $09 <DAD B>
ADD HL,DE $19 <DAD D>
ADD HL,HL $29 <DAD H>
ADD HL,SP $39 <DAD SP>
Add the specified double register to the HL pair. The result is placed in HL. This is a double-precision addition. The carry flag is set if an overflow occurs. The instruction ADD HL,HL performs a 16-bit arithmetic shift left, effectively doubling the value in HL. The ADD HL,SP instruction can be used with the 8080 CPU to save an incoming stack pointer:
LXI H,0
DAD SP
SHLD nnnn
Flags affected: C, H, O, S, Z
Flag reset: N
--------------------------------------------------
ADD IX,rr <no 8080>
ADD IY,rr <no 8080>
ADD IX,BC $DD $09
ADD IX,DE $DD $19
ADD IX,IX $DD $29
ADD IX,SP $DD $39
ADD IY,BC $FD $09
ADD IY,DE $FD $19
ADD IY,IY $FD $29
ADD IY,SP $FD $39
Add the indicated double register to the specified index register. The result is placed in the index register. The HL register pair does not participate in this group of instructions. Notice that there is no equivalent series of ADC instructions.
Flags affected: C, O, S, Z
Flag reset: N
--------------------------------------------------
AND (HL) [1/7] <ANA M> [1/7]
AND (HL) $A6 <ANA M>
Perform a logical AND with the accumulator and the memory location pointed to by the HL register pair. The result is placed in the accumulator.
Flags affected: P, S, Z
Flags reset: C, N
Flag set: H
--------------------------------------------------
AND (IX+dd) [3/19] <no 8080>
AND (IY+dd) [3/19] <no 8080>
AND (IX+dd) $DD $A6 dd
AND (IY+dd) $FD $A6 dd
Perform a logical AND with the accumulator and the memory byte referenced by the sum of the index register and displacement. The result is placed in the accumulator.
Flags affected: P, S, Z
Flags reset: C, N
Flag set: H
--------------------------------------------------
AND r [1/4] <ANA r> [1/4]
AND A $A7 <ANA A>
AND B $A0 <ANA B>
AND C $A1 <ANA C>
AND D $A2 <ANA D>
AND E $A3 <ANA E>
AND H $A4 <ANA H>
AND L $A5 <ANA L>
Perform a logical AND with the accumulator and register r. The result is placed in the accumulator. An instruction AND A is an effective way to test the parity, sign, and zero flags.
Flags affected: P, S, Z
Flags reset: C, N
Flag set: H
--------------------------------------------------
AND nn [2/7] <ANI nn> [2/7]
AND nn $E6 nn <ANI nn>
Perform a logical AND with the accumulator and the constant given in the argument. The result is placed in the accumulator. This instruction can be used to selectively reset bits of the accumulator. For example, the instruction AND 7FH will reset bit 7.
Flags affected: P, S, Z
Flags reset: C, N
Flag set: H
--------------------------------------------------
BIT b,(HL) [2/12] <no 8080>
BIT b,(IX+dd) [4/20] <no 8080>
BIT b,(IY+dd) [4/20] <no 8080>
b BIT b,(HL) BIT b,(IX+dd) BIT b,(IY+dd)
-----------------------------------------------
0 $CB $46 $DD $CB $46 dd $FD $CB $46 dd
1 $CB $4E $DD $CB $4E dd $FD $CB $46 dd
2 $CB $56 $DD $CB $56 dd $FD $CB $56 dd
3 $CB $5E $DD $CB $5E dd $FD $CB $5E dd
4 $CB $66 $DD $CB $66 dd $FD $CB $66 dd
5 $CB $6E $DD $CB $6E dd $FD $CB $6E dd
6 $CB $76 $DD $CB $76 dd $FD $CB $76 dd
7 $CB $7E $DD $CB $7E dd $FD $CB $7E dd
Test bit b of the memory byte referenced by the second operand. Bit b can range from zero through 7. The zero flag is set if the referenced bit is a logical 1; otherwise, it is reset. Thus, the zero flag becomes the complement of the selected bit.
Flag affected: Z
Flag set: H
Flag reset: N
--------------------------------------------------
BIT b,r [2/8] <no 8080>
b BIT b,A BIT b,B BIT b,C BIT b,D BIT b,E BIT b,H BIT b,L
-----------------------------------------------------------------------
0 $CB $47 $CB $40 $CB $41 $CB $42 $CB $43 $CB $44 $CB $45
1 $CB $4F $CB $48 $CB $49 $CB $4A $CB $4B $CB $4C $CB $4D
2 $CB $57 $CB $50 $CB $51 $CB $52 $CB $53 $CB $54 $CB $55
3 $CB $5F $CB $58 $CB $59 $CB $5A $CB $5B $CB $5C $CB $5D
4 $CB $67 $CB $60 $CB $61 $CB $62 $CB $63 $CB $64 $CB $65
5 $CB $6F $CB $68 $CB $69 $CB $6A $CB $6B $CB $6C $CB $6D
6 $CB $77 $CB $70 $CB $71 $CB $72 $CB $73 $CB $74 $CB $75
7 $CB $7F $CB $78 $CB $79 $CB $7A $CB $7B $CB $7C $CB $7D
Test bit b of register r, where b can range from zero through 7. The zero flag is set if the referenced bit is a logical 1. It is reset otherwise.
Flag affected: Z
Flag set: H
Flag reset: N
--------------------------------------------------
CALL nnnn [3/17] <CALL nnnn> [3/17]
CALL nnnn $CD nnnn <CALL nnnn>
Unconditional subroutine call to address nnnn. The address of the following instruction is pushed onto the stack.
Flags affected: none
--------------------------------------------------
CALL f,nnnn [3/17/10] <CC nnnn> [3/17/11]
CALL C,nnnn $DC nn nn <CC nnnn>
CALL M,nnnn $FC nn nn <CM nnnn>
CALL NC,nnnn $D4 nn nn <CNC nnnn>
CALL NZ,nnnn $C4 nn nn <CNZ nnnn>
CALL P,nnnn $F4 nn nn <CP nnnn>
CALL PE,nnnn $EC nn nn <CPE nnnn>
CALL PO,nnnn $E4 nn nn <CPO nnnn>
CALL Z,nnnn $CC nn nn <CZ nnnn>
Conditional subroutine call to address nnnn. The address of the following instruction is pushed onto the stack. The conditions are:
C carry flag set (carry)
M sign flag set (minus)
NC carry flag reset (not carry)
NZ zero flag reset (not zero)
P sign flag reset (plus)
PE parity flag set (parity even)
PO parity flag reset (parity odd)
Z zero flag set (zero)
--------------------------------------------------
CCF [1/4] <CMC> [1/4]
CCF $3F <CMC>
Complement the carry flag. This instruction can be given after a SCF command to reset the carry flag.
Flag affected: C
Flag reset: N
--------------------------------------------------
CP (HL) [1/7] <CMP M> [1/7]
CP (HL) $BE <CMP M>
Compare the byte in memory pointed to by the HL pair to the accumulator (an implied operand). The zero flag is set if the accumulator is equal to the operand. The carry flag is set if the accumulator is smaller than the operand.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
CP (IX+dd) [3/19] <no 8080>
CP (IY+dd) [3/19] <no 8080>
CP (IX+dd) $DD $BE dd
CP (IY+dd) $FD $BE dd
Compare the memory location referenced by the sum of the index register and displacement to the accumulator which is an implied operand. The zero flag is set if the accumulator is equal to the operand. The carry flag is set if the accumulator is smaller than the operand.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
CP r [1/4] <CMP r> [1/4]
CP A $BF <CMP A>
CP B $B8 <CMP B>
CP C $B9 <CMP C>
CP D $BA <CMP D>
CP E $BB <CMP E>
CP H $BC <CMP H>
CP L $BD <CMP L>
CP M $BE <CMP M>
Compare register r to the accumulator, which is an implied operand. The zero flag is set if the accumulator is equal to the operand. The carry flag is set if the accumulator is smaller than the operand.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
CP nn [2/7] <CPI nn> [2/7]
CP nn $FE nn <CPI nn>
Compare the constant given in the operand to the accumulator, which is an implied operand. The zero flag is set if the accumulator is equal to the operand. The carry flag is set if the accumulator is smaller than the operand.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
CPD [2/16] <no 8080>
CPDR [2/16] <no 8080>
CPI [2/16] <no 8080>
CPIR [2/16] <no 8080>
CPD $ED $A9
CPDR $ED $B9
CPI $ED $A1
CPIR $ED $B1
Compare the memory byte pointed to by HL to the accumulator. Decrement HL (if D) or increment HL (if I). Decrement the byte count in the BC register. Repeat the operation for CPDR and CPIR until a match is found or until the BC register pair has been decremented to zero. The zero flag is set if a match is found. The parity flag is set if BC is decremented to zero.
Flags affected: H, S
Flags set: N, Z if A = (HL), P if BC = 0
--------------------------------------------------
CPL [1/4] <CMA> [1/4]
CPL $2F <CMA>
Complement the accumulator. This instruction performs a one's comple^ ment on the accumulator. (Compare to the instruction NEG.)
Flags set: H, N
--------------------------------------------------
DAA [1/4] <DAA> [1/4]
DAA $27 <DAA>
Decimal adjust the accumulator. This instruction is used after each addition with BCD numbers. The Z-80 performs this operation properly for both addition and subtraction. The 8080, however, gives an incorrect result for subtraction.
Flags affected: O, S, Z, C, H
--------------------------------------------------
DEC (HL) [1/11] <DCR M> [1/10]
DEC (HL) $35 <DCR M>
Decrement the memory byte pointed to by the HL register pair.
Flags affected: H, O, S, Z
Flag set: N
Flag not affected: C
--------------------------------------------------
DEC (IX+dd) [3/23] <no 8080>
DEC (IY+dd) [3/23] <no 8080>
DEC (IX+dd) $DD $35 dd
DEC (IY+dd) $FD $35 dd
Decrement the memory byte pointed to by the sum of the index register and the displacement.
Flags affected: H, 0, S, Z
Flag set: N
Flag not affected: C
--------------------------------------------------
DEC r [1/4] <DCR r> [1/4]
DEC A $3D <DCR A>
DEC B $05 <DCR B>
DEC C $0D <DCR C>
DEC D $15 <DCR D>
DEC E $1D <DCR E>
DEC H $25 <DCR H>
DEC L $2D <DCR L>
DEC M $35 <DCR M>
Decrement the register r. Don't try to decrement a register past zero while executing a JP NC loop. The carry flag is not affected by this operation.
Flags affected: H, O, S, Z
Flag set: N
Flag not affected: C
--------------------------------------------------
DEC rr [1/6] <DCX B> [1/5]
DEC BC $0B <DCX B>
DEC DE $1B <DCX D>
DEC HL $2B <DCX H>
DEC SP $3B <DCX SP>
Decrement the indicated double register. Don't try to decrement a double register to zero in a JP NZ loop. It won't work since this operation does not affect any of the PSW flags. Instead, move one byte of the double register into the accumulator and perform a logical OR with the other byte.
LD A,C
OR B
JR NZ,nnnn
Flags affected: none!!!!
--------------------------------------------------
DEC IX [2/10] <no 8080>
DEC IY [2/10] <no 8080>
DEC IX $DD $2B
DEC IY $FD $2B
Decrement the index register.
Flags affected: none
--------------------------------------------------
DI [1/4] <DI> [1/4]
DI $F3 <DI>
Disable maskable interrupt request.
--------------------------------------------------
DJNZ dd [2/13/8] <no 8080>
DJNZ dd $10 dd
Decrement register B and jump relative to displacement dd if B register is not zero.
Flags affected: none
--------------------------------------------------
EI [1/4] <EI> [1/4]
EI $FB <EI>
Enable maskable interrupt request.
--------------------------------------------------
EX (SP),HL [1/19] <XTHL> [1/18]
EX (SP),HL $E3 <XTHL>
Exchange the byte at the stack pointer with register L. Exchange the byte at the stack pointer + 1 with register H.
Flags affected: none
--------------------------------------------------
EX (SP),IX [2/23] <no 8080>
EX (SP),IY [2/23] <no 8080>
EX (SP),IX $DD $E3
EX (SP),IY $FD $E3
Exchange the 16 bits referenced by the stack pointer with the specified index register.
Flags affected: none
--------------------------------------------------
EX AF,AF' [1/4] <no 8080>
EX AF,AF' $08
Exchange the accumulator and flag register with the alternate set.
Flags affected: all
--------------------------------------------------
EX DE,HL [1/4] <XCHG> [1/5]
EX DE,HL $EB <XCHG>
Exchange the double registers DE and HL.
Flags affected: none
--------------------------------------------------
EXX [1/4] <no 8080>
EXX $D9
Exchange BC, DE, and HL with the alternate set.
Flags affected: none
--------------------------------------------------
HALT [1/4] <HLT> [1/4]
HALT $76 <HLT>
Suspend operation of the CPU until a reset or interrupt occurs. Dynamic memory refresh continues during a halt.
--------------------------------------------------
IM # [2/8] <no 8080>
IM 0 $ED $46
IM 1 $ED $56
IM 2 $ED $5E
Sets interrupt mode 0, 1, or 2. Interrupt mode 0 is automatically selected when a Z-80 reset occurs. The result is the same as the 8080 interrupt response. Interrupt mode 1 performs an RST 38H instruction. Interrupt mode 2 provides for many interrupt locations.
--------------------------------------------------
IN r,(C) [2/12] <no 8080>
IN A,(C) $ED $78
IN B,(C) $ED $40
IN C,(C) $ED $48
IN D,(C) $ED $50
IN E,(C) $ED $58
IN H,(C) $ED $60
IN L,(C) $ED $68
Input a byte from the port address in register C to register r.
Flags affected: P, S, Z
Flags reset: H, N
--------------------------------------------------
IN A,(nn) [2/11] <IN nn> [2/10]
IN A,(nn) $DB nn <IN nn>
Input a byte from the port address nn to the accumulator.
Flags affected: none
--------------------------------------------------
INC (HL) [1/11] <INR M> [1/10]
INC (HL) $34 <INR M>
Increment the memory byte pointed to by the HL pair.
Flags affected: H, 0, S, Z
Flag set: N
Flag not affected: C!!!!
--------------------------------------------------
INC (IX+dd) [3/23] <no 8080>
INC (IY+dd) [3/23] <no 8080>
INC (IX+dd) $DD $34
INC (IY+dd) $FD $34
Increment the memory byte pointed to by the sum of the index register and the displacement.
Flags affected: H, O, S, Z
Flag set: N
Flag not affected: C!!!
--------------------------------------------------
INC r [1/4] <INR r> [1/5]
INC A $3C <INR A>
INC B $04 <INR B>
INC C $0C <INR C>
INC D $14 <INR D>
INC E $1C <INR E>
INC H $24 <INR H>
INC L $2C <INR L>
Increment the 8-bit register r. Don't try to increment a register past zero while executing a JP NC loop. It won't work because the carry flag is unaffected by this instruction.
Flags affected: H, O, S, Z
Flag set: N
Flag not affected: C!!!
--------------------------------------------------
INC rr [1/6] <INX rr> [1/5]
INC BC $03 <INX B>
INC DE $13 <INX D>
INC HL $23 <INX H>
INC SP $33 <INX SP>
Increment the specified double register.
Flags affected: none!!!!
--------------------------------------------------
INC IX [2/10] <no 8080>
INC IY [2/10] <no 8080>
INC IX $DD $23
INC IY $FD $23
Increment the specified index register.
Flags affected: none
--------------------------------------------------
IND [2/16] <no 8080>
INDR [2/21/16] <no 8080>
INI [2/16] <no 8080>
INIR [2/21/16] <no 8080>
IND $ED $AA
INDR $ED $BA
INI $ED $A2
INIR $ED $B2
Input a byte from the port address in register C to the memory byte pointed to by HL. Decrement register B. The HL register is incremented (if I) or decremented (if D). For INDR and INIR the process is repeated until the 8-bit register B becomes zero.
Flag affected: Z(ifB = 0)
Flag set: N
--------------------------------------------------
JP (HL) [1/4] <PCHL> [1/5]
JP (HL) $E9 <PCHL>
Copy the HL register pair into the program counter; then retrieve the next instruction from the address referenced by HL. This instruction causes a jump to the address referenced by HL.
Flags affected: none
--------------------------------------------------
JP (IX) [2/8] <no 8080>
JP (IY) [2/8] <no 8080>
JP (IX) $DD $E9
JP (IY) $FD $E9
Copy the contents of the specified index register into the program counter; then retrieve the next instruction from the address referenced by IX or IY.
Flags affected: none
--------------------------------------------------
JP nnnn [3/10] <JMP nnnn> [3/10]
JP nnnn $C3 nnnn <JMP nnnn>
Unconditional jump to address nnnn. Flags affected: none
--------------------------------------------------
JP f,nnnn [3/10] <JC nnnn> [3/10]
JP C,nnnn $DA nn nn <JC nnnn>
JP M,nnnn $FA nn nn <JM nnnn>
JP NC,nnnn $D2 nn nn <JNC nnnn>
JP NZ,nnnn $C2 nn nn <JNZ nnnn>
JP P,nnnn $F2 nn nn <JP nnnn>
JP PE,nnnn $EA nn nn <JPE nnnn>
JP PO,nnnn $E2 nn nn <JPO nnnn>
JP Z,nnnn $CA nn nn <JZ nnnn>
Conditional jump to address nnnn where:
C means carry flag set (carry)
M means sign flag set (minus)
NC means carry flag reset (not carry)
NZ means zero flag reset (not zero)
P means sign flag reset (plus)
PE means parity flag set (parity even)
PO means parity flag reset (parity odd)
Z means zero flag set (zero)
--------------------------------------------------
JR dd [2/12] <no 8080>
JR dd $18 dd
Unconditional relative jump with a signed displacement nn. The jump is limited to 129 bytes forward and 126 bytes backward in memory.
Flags affected: none
--------------------------------------------------
JR C,dd [2/12/7] <no 8080>
JR NC,dd [2/12/7] <no 8080>
JR NZ,dd [2/12/7] <no 8080>
JR Z,dd [2/12/7] <no 8080>
JR C,dd $38 dd
JR NC,dd $30 dd
JR NZ,dd $20 dd
JR Z,dd $28 dd
Conditional relative jump to address nn where:
C means carry flag set (carry)
NC means carry flag reset (not carry)
NZ means zero flag reset (not zero)
Z means zero flag set (zero)
--------------------------------------------------
LD (BC),A [1/7] <STAX B> [1/7]
LD (DE),A [1/7] <STAX D> [1/7]
LD (BC),A $02 <STAX B>
LD (DE),A $12 <STAX D>
Move the byte in the accumulator to the memory byte referenced by the specified register pair.
--------------------------------------------------
LD (HL),r [1/7] <MOV M,r> [1/7]
LD (HL),A $77 <MOV M,A>
LD (HL),B $70 <MOV M,B>
LD (HL),C $71 <MOV M,C>
LD (HL),D $72 <MOV M,D>
LD (HL),E $73 <MOV M,E>
LD (HL),H $74 <MOV M,H>
LD (HL),L $75 <MOV M,L>
Move the byte in register r to the memory byte pointed to by the HL pair.
--------------------------------------------------
LD (HL),nn [2/10] <MVI M,nn> [2/10]
LD (HL),nn $36 nn <MVI M,nn>
Move the immediate byte nn into the memory byte referenced by the HL pair.
--------------------------------------------------
LD (IX+dd),r [3/19] <no 8080>
LD (IX+dd),nn [4/19] <no 8080>
LD (IY+dd),r [3/19] <no 8080>
LD (IY+dd),nn [4/19] <no 8080>
LD (IX+dd),A $DD $77 dd
LD (IX+dd),B $DD $70 dd
LD (IX+dd),C $DD $71 dd
LD (IX+dd),D $DD $72 dd
LD (IX+dd),E $DD $73 dd
LD (IX+dd),H $DD $74 dd
LD (IX+dd),L $DD $75 dd
LD (IX+dd),nn $DD $36 dd nn
LD (IY+dd),A $FD $77 dd
LD (IY+dd),B $FD $70 dd
LD (IY+dd),C $FD $71 dd
LD (IY+dd),D $FD $72 dd
LD (IY+dd),E $FD $73 dd
LD (IY+dd),H $FD $74 dd
LD (IY+dd),L $FD $75 dd
LD (IY+dd),nn $FD $36 dd nn
Move the byte in register r or the immediate byte nn into the memory byte referenced by the sum of the index register plus the displacement. These instructions can be used to load relocatable binary code.
--------------------------------------------------
LD (nnnn),A [3/13] <STA nnnn> [3/13]
LD (nnnn),A $32 nn nn <STA nnnn>
Store the accumulator in the memory location referenced by nnnn.
--------------------------------------------------
LD (nnnn),BC [4/20] <no 8080>
LD (nnnn),DE [4/20] <no 8080>
LD (nnnn),BC $ED $43 nn nn
LD (nnnn),DE $ED $53 nn nn
Store the low-order byte (C or E) of the specified double register at the memory location nnnn. Store the high-order byte (B or D) at nnnn + 1.
--------------------------------------------------
LD (nnnn),HL [3/16] <SHLD nnnn> [3/16]
LD (nnnn),HL $22 nn nn <SHLD nnnn>
Store register L at the memory address nnnn. Store register H at the address nnnn + 1.
--------------------------------------------------
LD (nnnn),IX [4/20] <no 8080>
LD (nnnn),IY [4/20] <no 8080>
LD (nnnn),SP [4/20] <no 8080>
LD (nnnn),IX $DD $22 nn nn
LD (nnnn),IY $FD $22 nn nn
LD (nnnn),SP $ED $73 nn nn
Store the low-order byte of the specified register IX, IY, or SP at the location nnnn. Store the high-order byte at nnnn + 1. The instruction LD (nnnn),SP can be used to temporarily save an incoming stack pointer. It can later be restored by a LD SP,(nnnn) operation.
--------------------------------------------------
LD A,(BC) [1/7] <LDAX B> [1/7]
LD A,(DE) [1/7] <LDAX D> [1/7]
LD A,(BC) $0A <LDAX B>
LD A,(DE) $1A <LDAX D>
Move the memory byte referenced by the specified register pair BC or DE into the accumulator.
--------------------------------------------------
LD A,I [2/9] <no 8080>
LD A,I $ED $57
Load the accumulator from the interrupt-vector register. The parity flag reflects the state of the interrupt-enable flip-flop.
Flags affected: S, Z, P
Flags reset: H, N
--------------------------------------------------
LD A,R [2/9] <no 8080>
LD A,R $ED $5F
Load the accumulator from the memory-refresh register. The parity flag reflects the state of the interrupt-enable flip-flop. This is an easy way to obtain a fairly decent random number.
Flags affected: S, Z, P
Flags reset: H, N
--------------------------------------------------
LD I,A [2/9] <no 8080>
LD I,A $ED $47
Copy the accumulator into the interrupt-vector register.
Flags affected: none
--------------------------------------------------
LD R,A [2/9] <no 8080>
LD R,A $ED $4F
Copy the accumular into memory-refresh register.
Flags affected: none
--------------------------------------------------
LD r,(HL) [1/7] <MOV r,M> [1/7]
LD A,(HL) $7E <MOV A,M>
LD B,(HL) $46 <MOV B,M>
LD C,(HL) $4E <MOV C,M>
LD D,(HL) $56 <MOV D,M>
LD E,(HL) $5E <MOV E,M>
LD H,(HL) $66 <MOV H,M>
LD L,(HL) $6E <MOV L,M>
Move the byte in the memory location pointed to by the HL register pair into register r.
--------------------------------------------------
LD r,(IX+dd) [3/19] <no 8080>
LD r,(IY+dd) [3/19] <no 8080>
LD A,(IX+dd) $DD $7E dd
LD B,(IX+dd) $DD $46 dd
LD C,(IX+dd) $DD $4E dd
LD D,(IX+dd) $DD $56 dd
LD E,(IX+dd) $DD $5E dd
LD H,(IX+dd) $DD $66 dd
LD L,(IX+dd) $DD $6E dd
Move the byte at the memory location referenced by the sum of the index register and the displacement into register r.
--------------------------------------------------
LD r,r2 [1/4] <MOV r,r2> [1/5]
Z-80 A B C D E H L 8080
----------------------------------------------------
LD A,r $7F $78 $79 $7A $7B $7C $7D MOV A,r
LD B,r $47 $40 $41 $42 $43 $44 $45 MOV B,r
LD C,r $4F $48 $49 $4A $4B $4C $4D MOV C,r
LD D,r $57 $50 $51 $52 $53 $54 $55 MOV D,r
LD E,r $5F $58 $59 $5A $5B $5C $5D MOV E,r
LD H,r $67 $60 $61 $62 $63 $64 $65 MOV H,r
LD L,r $6F $68 $69 $6A $6B $6C $6D MOV L,r
Move the byte from register r2 to r.
--------------------------------------------------
LD r,nn [2/7] <MVI r,nn> [2/7]
LD A,nn $3E nn <MVI A,nn>
LD B,nn $06 nn <MVI B,nn>
LD C,nn $0E nn <MVI C,nn>
LD D,nn $16 nn <MVI D,nn>
LD E,nn $1E nn <MVI E,nn>
LD H,nn $26 nn <MVI H,nn>
LD L,nn $2E nn <MVI L,nn>
Load register r with the 8-bit data byte nn.
--------------------------------------------------
LD A,(nnnn) [3/13] <LDA nnnn> [3/13]
LD A,(nnnn) $3A nn nn <LDA nnnn>
Load the accumulator from the memory byte referenced by the 16-bit pointer nnnn.
--------------------------------------------------
LD BC,(nnnn) [4/20] <no 8080>
LD BE,(nnnn) [4/20] <no 8080>
LD BC,(nnnn) $ED $4B nn nn
LD BE,(nnnn) $ED $5B nn nn
Load the low-order byte (C or E) from the location referenced by the 16-bit pointer nnnn. Load the high-order byte (B or D) from nnnn + 1.
--------------------------------------------------
LD HL,(nnnn) [3/16] <LHLD nnnn> [3/16]
LD HL,(nnnn) $2A nnnn <LHLD nnnn>
Load register L from the address referenced by the 16-bit value nnnn. Load register H from the address nnnn + 1.
--------------------------------------------------
LD BC,nnnn [3/10] <LXI rr,nnnn> [3/10]
LD BC,nnnn $01 nn nn <LXI B,nnnn>
LD DE,nnnn $11 nn nn <LXI D,nnnn>
LD HL,nnnn $21 nn nn <LXI H,nnnn>
LD SP,nnnn $31 nn nn <LXI SP,nnnn>
LD IX,nnnn $DD $21 nn nn
LD IY,nnnn $FD $21 nn nn
Load the specified double register with the 16-bit constant nnnn. Be careful not to confuse LD HL,(nnnn) with LD HL,nnnn.
--------------------------------------------------
LD IX,(nnnn) [4/20] <no 8080>
LD IY,(nnnn) [4/20] <no 8080>
LD SP,(nnnn) [4/20] <no 8080>
LD IX,(nnnn) $DD $2A nn nn
LD IY,(nnnn) $FD $2A nn nn
LD SP,(nnnn) $ED $7B nn nn
Load the low byte of IX, IY, or SP from the memory location nnnn. Load the high byte from nnnn + 1. The LD SP,(nnnn) instruction can be used to retrieve a previously saved stack pointer.
--------------------------------------------------
LD SP,HL [1/6] <SPHL>
LD SP,IX [2/10] <no 8080>
LD SP,IY [2/10] <no 8080>
LD SP,HL $F9 <SPHL>
LD SP,IX $DD $F9
LD SP,IY $FD $F9
Load the stack pointer from the specified 16-bit register. The SPHL instruction can be used to retrieve a previously saved stack pointer when the 8080 CPU is used.
LHLD nnnn
SPHL
--------------------------------------------------
LDD [2/16] <no 8080>
LDDR [2/21/16] <no 80B0>
LDI [2/16] <no 8080>
LDIR [2/21/16] <no 8080>
LDD $ED $A8
LDDR $ED $B8
LDI $ED $A0
LDIR $ED $B0
Move the byte referenced by the HL pair into the location pointed to by the DE register pair. Decrement the 16-bit byte counter in BC. Increment (if I) or decrement (if D) both HL and DE. Repeat the operation for LDDR and LDIR until the BC register has been decremented to zero.
--------------------------------------------------
NEG [2/8] <no 8080>
NEG $ED $44
This instruction performs a two's complement on the accumulator. It effectively subtracts the accumulator from zero. To perform this task on an 8080, use a CMA command followed by an INR A command.
Flags affected: all
--------------------------------------------------
NOP [1/4] <NOP> [1/4]
NOP $00 <NOP>
No operation is performed by the CPU.
Flags affected: none
--------------------------------------------------
OR (HL) [1/7] <ORA M> [1/7]
OR (HL) $B6 <ORA M>
Perform a logical OR with the accumulator and the byte referenced by HL. The result is placed in the accumulator.
Flags affected: P, S, Z
Flags reset: C, H, N
--------------------------------------------------
OR (IX+dd) [3/19] <no 8080>
OR (IY+dd) [3/19] <no 8080>
OR (IX+dd) $DD $B6 dd
OR (IY+dd) $FD $B6 dd
Perform a logical OR with the accumulator and the byte referenced by the specified index register plus the displacement. The result is placed in the accumulator.
Flags affected: P, S, Z
Flags reset: C, H, N
--------------------------------------------------
OR r [1/4] <ORA r> [1/4]
OR A $B7 <ORA A>
OR B $B0 <ORA B>
OR C $B1 <ORA C>
OR D $B2 <ORA D>
OR E $B3 <ORA E>
OR H $B4 <ORA H>
OR L $B5 <ORA L>
Perform a logical OR with the accumulator and the register r. The result is placed in the accumulator. An instruction of OR A is an efficient way to test the parity, sign, and zero flags.
Flags affected: P, S, Z
Flags reset: C, H, N
--------------------------------------------------
OR nn [2/7] <ORI nn> [2/7]
OR nn $F6 nn <ORI nn>
Perform a logical OR with the accumulator and the byte nn. The result is placed in the accumulator. This instruction can be used to set individual bits of the accumulator. For example, OR 20H will set bit 5 to a logical 1.
Flags affected: P, S, Z
Flags reset: C, H, N
--------------------------------------------------
OTDR [2/21/16] <no 8080>
OTIR [2/21/16] <no 8080>
OTDR $ED $BB
OTIR $ED $B3
Output a byte from the memory location pointed to by the HL pair. The port address is contained in register C. Register B is decremented. The HL register pair is incremented (if I) or decremented (if D). The process is repeated until register B has become zero.
Flags set: N, Z
--------------------------------------------------
OUT (C),r [2/12] <no 8080>
OUT (C),A $ED $79
OUT (C),B $ED $41
OUT (C),C $ED $49
OUT (C),D $ED $51
OUT (C),E $ED $59
OUT (C),H $ED $61
OUT (C),L $ED $69
Output the byte in register r to the port address contained in register C.
Flags affected: none
--------------------------------------------------
OUT (nn),A [2/11] <OUT nn> [2/10]
OUT (nn),A $D3 nn <OUT nn>
Output the byte in the accumulator to the port address nn.
Flags affected: none
--------------------------------------------------
OUTD [2/16] <no 8080>
OUTI [2/16] <no 8080>
OUTD $ED $AB
OUTI $ED $A3
Output a byte from the memory location pointed to by the HL pair. The port address is contained in register C. Register B is decremented. The HL register pair is incremented (if I) or decremented (if D).
Flag affected: Z
Flag set: N
--------------------------------------------------
POP AF [1/10] <POP PSW> [1/10]
POP AF $F1 <POP PSW>
Move the byte at the memory location referenced by the stack pointer into the flag register (PSW), and increment the stack pointer. Then move the byte at the location referenced by the new stack-pointer value into the accumulator and increment the stack pointer a second time.
Flags affected: all
--------------------------------------------------
POP BC [1/10] <POP B> [1/10]
POP DE [1/10] <POP D> [1/10]
POP HL [1/10] <POP H> [1/10]
POP BC $C1 <POP B>
POP DE $D1 <POP D>
POP HL $E1 <POP H>
Copy two bytes of memory into the appropriate double register as follows. The memory byte referenced by the stack pointer is moved into the low-order byte (C, E, or L), then the stack pointer is incremented. The memory byte referenced by the new stack pointer is then moved into the high-order byte (B, D, or H). The stack pointer is incremented a second time.
Flags affected: none
--------------------------------------------------
POP IX [2/14] <no 8080>
POP IY [2/14] <no 8080>
POP IX $DD $E1
POP IY $FD $E1
Copy the top of the stack into the specified index register. Increment the stack pointer twice.
Flags affected: none
--------------------------------------------------
PUSH AF [1/11] <PUSH PSW> [1/11]
PUSH AF $F5 <PUSH PSW>
Store the accumulator and flag register in memory as follows. The stack pointer is decremented, then the value in the accumulator is moved to the memory byte referenced by the stack pointer. The stack pointer is decremented a second time. The flag register is copied to the byte at the memory address referenced by the current stack-pointer position.
Flags affected: none
--------------------------------------------------
PUSH BC [1/11] <PUSH B> [1/11]
PUSH DE [1/11] <PUSH D> [1/11]
PUSH HL [1/11] <PUSH H> [1/11]
PUSH BC $C5 <PUSH B>
PUSH DE $D5 <PUSH D>
PUSH HL $E5 <PUSH H>
Store the referenced double register in memory as follows. The stack pointer is decremented, then the byte in the specified high-order register B, D, or H is copied to the memory location referenced by the stack pointer. The stack pointer is decremented a second time. The byte in the low-order position C, E, or L is moved to the byte referenced by the current value of the stack pointer.
Flags affected: none
--------------------------------------------------
PUSH IX [2/15] <no 8080>
PUSH IY [2/15] <no 8080>
PUSH IX $DD $E5
PUSH IY $FD $E5
The indicated index register is copied to the top of the stack. The stack pointer is decremented twice.
Flags affected: none
--------------------------------------------------
RES b,(HL) [2/15] <no 8080>
RES b,(IX+dd) [4/23] <no 8080>
RES b,(IY+dd) [4/23] <no 8080>
b RES b,(HL) RES b,(IX+dd) RES b,(IY+dd)
-----------------------------------------------
0 $CB $86 $DD $CB $86 dd $FD $CB $86 dd
1 $CB $8E $DD $CB $8E dd $FD $CB $8E dd
2 $CB $96 $DD $CB $96 dd $FD $CB $96 dd
3 $CB $9E $DD $CB $9E dd $FD $CB $9E dd
4 $CB $A6 $DD $CB $A6 dd $FD $CB $A6 dd
5 $CB $AE $DD $CB $AE dd $FD $CB $AE dd
6 $CB $B6 $DD $CB $B6 dd $FD $CB $B6 dd
7 $CB $BE $DD $CB $BE dd $FD $CB $BE dd
Reset bit b of the memory byte referenced by the second operand. Bit b can range from zero through 7.
Flag reset: N
Other flags affected: none
--------------------------------------------------
RES b,r [2/8] <no 8080>
b RES b,A RES b,B RES b,C RES b,D RES b,E RES b,H RES b,L
-----------------------------------------------------------------------
0 $CB $87 $CB $80 $CB $81 $CB $82 $CB $83 $CB $84 $CB $85
1 $CB $8F $CB $88 $CB $89 $CB $8A $CB $8B $CB $8C $CB $8D
2 $CB $97 $CB $90 $CB $91 $CB $92 $CB $93 $CB $94 $CB $95
3 $CB $9F $CB $98 $CB $99 $CB $9A $CB $9B $CB $9C $CB $9D
4 $CB $A7 $CB $A0 $CB $A1 $CB $A2 $CB $A3 $CB $A4 $CB $A5
5 $CB $AF $CB $A8 $CB $A9 $CB $AA $CB $AB $CB $AC $CB $AD
6 $CB $B7 $CB $B0 $CB $B1 $CB $B2 $CB $B3 $CB $B4 $CB $B5
7 $CB $BF $CB $B8 $CB $B9 $CB $BA $CB $BB $CB $BC $CB $BD
Reset bit b of register r to a value of zero. Bit b can range from zero through 7.
Flag reset: N
Other flags affected: none
--------------------------------------------------
RET [1/10] <RET> [1/10]
RET $C9 <RET>
Return from a subroutine. The top of the stack is moved into the program counter. The stack pointer is incremented twice.
--------------------------------------------------
RET C [1/11/5] <RC> [1/11/5]
RET M [1/11/5] <RM> [1/11/5]
RET NC [1/11/5] <RNC> [1/11/5]
RET NZ [1/11/5] <RNZ> [1/11/5]
RET P [1/11/5] <RP> [1/11/5]
RET PE [1/11/5] <RPE> [1/11/5]
RET PO [1/11/5] <RPO> [1/11/5]
RET Z [1/11/5] <RZ> [1/11/5]
RET C $D8 <RC>
RET M $F2 <RM>
RET NC $D0 <RNC>
RET NZ $C0 <RNZ>
RET P $F0 <RP>
RET PE $E8 <RPE>
RET PO $E0 <RPO>
RET Z $C8 <RZ>
Conditional return from a subroutine. If the condition is met, the top of the stack is moved into the program counter. The stack pointer is incremented twice.
C means carry flag set (carry)
M means sign flag set (minus)
NC means carry flag reset (not carry)
NZ means zero flag reset (not zero)
P means sign flag reset (plus)
PE means parity flag set (parity even)
PO means parity flag reset (parity odd)
Z means zero flag set (zero)
--------------------------------------------------
RETI [2/14] <no 8080>
RETI $ED $4D
Return from maskable interrupt.
--------------------------------------------------
RETN [2/14] <no 8080>
RETN $ED $45
Return from nonmaskable interrupt.
--------------------------------------------------
The following RL and RLA instructions rotate bits to the left through carry.
!->---------->-------------->-------------->--------!
! !
! !---! !---!---!---!---!---!---!---!---! !
!--! ! <-----<- <- <- <- <- <- <- <- ! <-!
!---! !---!---!---!---!---!---!---!---!
carry register
--------------------------------------------------
RL (HL) [2/15] <no 8080>
RL (HL) $CB $16
The memory byte referenced by the HL pair is rotated left through carry. The carry flag moves into bit zero. Bit 7 moves to the carry flag.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RL (IX+dd) [4/23] <no 8080>
RL (IY+dd) [4/23] <no 8080>
RL (IX+dd) $DD $CB $16 dd
RL (IY+dd) $FD $CB $16 dd
The memory byte referenced by the sum of the index register and the displacement is rotated left through carry. The carry flag moves into bit zero. Bit 7 moves to the carry flag.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RL r [2/8] <no 8080>
RL A $CB $17
RL B $CB $10
RL C $CB $11
RL D $CB $12
RL E $CB $13
RL H $CB $14
RL L $CB $15
The byte in register r is rotated left through carry. The carry flag moves into bit zero. Bit 7 moves to the carry flag. Note: the instruction RL A performs the same task that the separate instruction RLA does, but the former takes twice as long as the latter.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RLA [1/4] <RAL> [1/4]
RLA $17 <RAL>
The byte in the accumulator is rotated left through carry. The carry flag moves to bit zero. Bit 7 of the accumulator moves to the carry flag.
Flag affected: C
Flags reset: H, N
--------------------------------------------------
The following RLC and RLCA instructions rotate bits to the left.
!->------------->-------------->--------!
! !
!---! ! !---!---!---!---!---!---!---!---! !
! ! <--!--<- <- <- <- <- <- <- <- ! <-!
!---! !---!---!---!---!---!---!---!---!
carry register
--------------------------------------------------
RLC (HL) [2/15] <no 8080>
RLC (HL) $CB $06
The byte referenced by the HL pair is rotated left circularly. Bit 7 moves to both the zero bit and to the carry flag.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RLC (IX+dd) [4/23] <no 8080>
RLC (IY+dd) [4/23] <no 8080>
RLC (IX+dd) $DD $CB $06 dd
RLC (IY+dd) $FD $CB $06 dd
The byte referenced by the specified index register plus the displacement is rotated left circularly. Bit 7 moves to both bit zero and the carry flag.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RLC r [2/8] <no 8080>
RLC A $CB $07
RLC B $CB $00
RLC C $CB $01
RLC D $CB $02
RLC E $CB $03
RLC H $CB $04
RLC L $CB $05
The byte in register r is rotated left circularly. Bit 7 moves to both bit zero and the carry flag. Note: RLC A performs the same task that another instruction RLCA does, but the former instruction takes twice as long as the latter.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RLCA [1/4] <RLC> [1/4]
RLCA $07 <RLC>
The accumulator is rotated left circularly. Bit 7 moves to both bit zero and the carry flag.
Flag affected: C
Flags reset: H, N
--------------------------------------------------
RLD [2/18] <no 8080>
RLD $ED $6F
A 4-bit rotation over 12 bits. The low 4 bits of A move to the low 4 bits of the memory location referenced by the HL pair. The original low 4 bits of memory move to the high 4 bits. The original high 4 bits move to the low 4 bits of A. This instruction is used for BCD operations.
Flags affected: P, S, Z
Flags reset: H, N
!--<---<--! !-<----<-!
! ! ! !
!--------!--------! !--------!--------!
! 4 bits ! 4 bits ! ! 4 bits ! 4 bits !
!--------!--------! !--------!--------!
accumulator ! memory !
!-->-------->------>--!
--------------------------------------------------
The following RR and RRA instructions rotate bits to the right through carry.
!-----<---------<--------------<------------<-----!
! !
! !---!---!---!---!---!---!---!---! !---! !
!-> ! -> -> -> -> -> -> -> ->----> ! !-!
!---!---!---!---!---!---!---!---! !---!
register carry
--------------------------------------------------
RR (HL) [2/15] <no 8080>
RR (HL) $CB $1E
The memory byte pointed to by the HL pair is rotated right through carry. Carry moves to bit 7. Bit zero moves to the carry flag.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RR (IX+dd) [4/23] <no 8080>
RR (IY+dd) [4/23] <no 8080>
RR (IX+dd) $DD $CB $1E dd
RR (IY+dd) $FD $CB $1E dd
The memory byte pointed to by the specified index register plus the offset is rotated right through carry. The carry flag moves to bit 7. Bit zero moves to the carry flag.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RR r [2/8] <no 8080>
RR A $CB $1F
RR B $CB $10
RR C $CB $11
RR D $CB $12
RR E $CB $13
RR H $CB $14
RR L $CB $15
The byte in register r is rotated right through carry. Carry moves to bit 7. Bit zero moves to the carry flag. Note: RR A performs the same task that another instruction RRA does, but the former instruction takes twice as long as the latter.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RRA [1/4] <RAR> [1/4]
RRA $1F <RAR>
The accumulator is rotated right through carry. The carry flag moves to bit 7. Bit zero moves to the carry flag.
Flag affected: C
Flags reset: H, N
--------------------------------------------------
The following RRC and RRCA instructions rotate bits to the right.
!-----<---------------<--------------<--!
! !
! !---!---!---!---!---!---!---!---! ! !---!
!-> ! -> -> -> -> -> -> -> ->--!----> ! !
!---!---!---!---!---!---!---!---! !---!
register carry
--------------------------------------------------
RRC (HL) [2/15] <no 8080>
RRC (HL) $CB $0E
The memory byte pointed to by the HL pair is rotated right circularly. Bit zero moves to both the carry flag and bit 7.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RRC (IX+dd) [4/23] <no 8080>
RRC (IY+dd) [4/23] <no 8080>
RRC (IX+dd) $DD $CB $0E dd
RRC (IY+dd) $FD $CB $0E dd
The memory byte pointed to by the index register plus the offset is rotated right circularly. Bit zero moves to both the carry flag and bit 7.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RRC r [2/8] <no 8080>
RRC A $CB $0F
RRC B $CB $08
RRC C $CB $09
RRC D $CB $0A
RRC E $CB $0B
RRC H $CB $0C
RRC L $CB $0D
The byte in register r is rotated right circularly. Bit zero moves to both the carry flag and bit 7. Note: RRC A performs the same task that another instruction RRCA does, but the former instruction takes twice as long as the latter.
Flags affected: C, P, S, Z
Flags reset: H, N
--------------------------------------------------
RRCA [1/4] <RRC>
RRCA $0F <RRC>
The accumulator is rotated right circularly. Bit zero moves to both the carry flag and bit 7.
Flag affected: C
Flags reset: H, N
--------------------------------------------------
RRD [2/18] <no 8080>
RRD $ED $67
A 4-bit rotation over 12 bits. The low 4 bits of A move to the high 4 bits of the memory location referenced by the HL pair. The original high 4 bits of memory move to the low 4 bits. The original low 4 bits move to the low 4 bits of A. This instruction is used for BCD operations.
Flags affected: P, S, Z
Flags reset: H, N
!-->--->--! !->---->-!
! ! ! !
!--------!--------! !--------!--------!
! 4 bits ! 4 bits ! ! 4 bits ! 4 bits !
!--------!--------! !--------!--------!
accumulator ! memory !
!--<------<--------<--!
--------------------------------------------------
RST 00H [1/11] <RST 0> [1/11]
RST 08H <RST 1>
RST 10H <RST 2>
RST 18H <RST 3>
RST 20H <RST 4>
RST 28H <RST 5>
RST 30H <RST 6>
RST 38H <RST 7>
RST 00H $C7 <RST 0>
RST 08H $CF <RST 1>
RST 10H $D7 <RST 2>
RST 18H $DF <RST 3>
RST 20H $E7 <RST 4>
RST 28H $EF <RST 5>
RST 30H $F7 <RST 6>
RST 38H $FF <RST 7>
These restart instructions generate one-byte subroutine calls to address given in the Z-80 operand.
--------------------------------------------------
SBC A,(HL) [1/7] <SBB M> [1/7]
SBC A,(HL) $9E <SBB M>
Subtract the carry flag and the memory byte pointed to by the HL pair from the accumulator. The result is placed in the accumulator. Some Z-80 assemblers allow the 8080 mnemonic of SBB to be used as an alternate Z-80 mnemonic for this instruction.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SBC A,(IX+dd) [3/19] <no 8080>
SBC A,(IY+dd) [3/19] <no 8080>
SBC A,(IX+dd) $DD $9E dd
SBC A,(IY+dd) $FD $9E dd
Subtract the carry flag and the memory byte pointed to by the sum of the index register and displacement from the accumulator. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SBC A,r [1/4] <SBB r> [1/4]
SBC A,A $9F <SBB A>
SBC A,B $98 <SBB B>
SBC A,C $99 <SBB C>
SBC A,D $9A <SBB D>
SBC A,E $9B <SBB E>
SBC A,H $9C <SBB H>
SBC A,L $9D <SBB L>
Subtract the carry flag and the specified CPU register from the accumulator. The result is placed in the accumulator. Some Z-80 assemblers allow the 8080 mnemonic of SBB to be used as an alternate Z-80 mnemonic for this instruction.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SBC A,nn [2/7] <SBI nn> [2/7]
SBC A,nn $DE nn <SBI nn>
Subtract the immediate byte (the second operand) and the carry flag from the accumulator. The result is placed in the accumulator. Some Z-80 assemblers allow the 8080 mnemonic of SBB to be used as an alternate Z-80 mnemonic for this instruction.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SBC HL,rr [2/15] <no 8080>
SBC HL,BC $ED $42
SBC HL,DE $ED $52
SBC HL,HL $ED $62
SBC HL,SP $ED $72
Subtract the specified CPU double register and the carry flag from the HL register pair. The result is placed in HL. You may need to reset the carry flag with an OR A operation before using these instructions.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SCF [1/4] <STC> [1/4]
SCF $37 <STC>
Set the carry flag. There is no equivalent reset command. However, the carry flag can be reset with the XOR A instruction, or with the pair of instructions SCF and CCF.
Bit set: C
Bits reset: H, N
--------------------------------------------------
SET b,(HL) [2/15] <no 8080>
SET b,(IX+dd) [4/23] <no 8080>
SET b,(IY+dd) [4/23] <no 8080>
b SET b,(HL) SET b,(IX+dd) SET b,(IY+dd)
-----------------------------------------------
0 $BC $C6 $DD $CB $C6 dd $FD $CB $C6 dd
1 $BC $CE $DD $CB $CE dd $FD $CB $CE dd
2 $BC $D6 $DD $CB $D6 dd $FD $CB $D6 dd
3 $BC $DE $DD $CB $DE dd $FD $CB $DE dd
4 $BC $E6 $DD $CB $E6 dd $FD $CB $E6 dd
5 $BC $EE $DD $CB $EE dd $FD $CB $EE dd
6 $BC $F6 $DD $CB $F6 dd $FD $CB $F6 dd
7 $BC $FE $DD $CB $FE dd $FD $CB $FE dd
Set bit b of the memory byte referenced by the second operand. Bit b can range from zero through 7.
Flag reset: N
Other flags affected: none
--------------------------------------------------
SET b,r [2/8] <no 8080>
b SET b,A SET b,B SET b,C SET b,D SET b,E SET b,H SET b,L
-----------------------------------------------------------------------
0 $CB $C7 $CB $C0 $CB $C1 $CB $C2 $CB $C3 $CB $C4 $CB $C5
1 $CB $CF $CB $C8 $CB $C9 $CB $CA $CB $CB $CB $CC $CB $CD
2 $CB $D7 $CB $D0 $CB $D1 $CB $D2 $CB $D3 $CB $D4 $CB $D5
3 $CB $DF $CB $D8 $CB $D9 $CB $DA $CB $DB $CB $DC $CB $DD
4 $CB $E7 $CB $E0 $CB $E1 $CB $E2 $CB $E3 $CB $E4 $CB $E5
5 $CB $EF $CB $E8 $CB $E9 $CB $EA $CB $EB $CB $EC $CB $ED
6 $CB $F7 $CB $F0 $CB $F1 $CB $F2 $CB $F3 $CB $F4 $CB $F5
7 $CB $FF $CB $F8 $CB $F9 $CB $FA $CB $FB $CB $FC $CB $FD
Set bit b of register r. Bit b can range from zero through 7.
Flag reset: N
Other flags affected: none
--------------------------------------------------
The following SLA instructions shift bits to the left.
!---! !---!---!---!---!---!---!---!---!
! ! <-----<- <- <- <- <- <- <- <- ! <-- 0
!---! !---!---!---!---!---!---!---!---!
carry register
--------------------------------------------------
SLA (HL) [2/15] <no 8080>
SLA (HL) $CB $26
Perform an arithmetic shift left on the memory byte pointed to by the HL pair. Bit 7 is moved to the carry flag. A zero is moved into bit zero. This operation doubles the original value.
Bits affected: C, P, S, Z
Bits reset: H, N
--------------------------------------------------
SLA (IX+dd) [4/23] <no 8080>
SLA (IY+dd) [4/23] <no 8080>
SLA (IX+dd) $DD $CB $26 dd
SLA (IY+dd) $FD $CB $26 dd
Perform an arithmetic shift left on the memory byte pointed to by the index register plus the displacement. Bit 7 is moved to the carry flag. A zero is moved into bit zero. This operation doubles the original value.
Bits affected: C, P, S, Z
Bits reset: H, N
--------------------------------------------------
SLA r [2/8] <no 8080>
SLA A $CB $27
SLA B $CB $20
SLA C $CB $21
SLA D $CB $22
SLA E $CB $23
SLA H $CB $24
SLA L $CB $25
Perform an arithmetic shift left on register r. Bit 7 is moved to the carry flag. A zero is moved into bit zero. This operation doubles the original value. Note: SLA A performs the same task that another instruction ADD A,A does, but the former instruction takes twice as long as the latter.
Bits affected: C, P, S, Z
Bits reset: H, N
--------------------------------------------------
The following SRA instructions shift bits to the right.
!---!---!---!---!---!---!---!---! !---!
!-> ! -> -> -> -> -> -> -> ->-------> ! !
! !---!---!---!---!---!---!---!---! !---!
! ! register carry
!--<--!
--------------------------------------------------
SRA (HL) [2/15] <no 8080>
SRA (HL) $CB $2E
Perform an arithmetic shift right on the memory byte pointed to by the HL pair. Bit zero moves to the carry flag. Bit 7 is duplicated in bit 6.
Bits affected: C, P, S, Z
Bits reset: H, N
--------------------------------------------------
SRA (IX+dd) [4/23] <no 8080>
SRA (IY+dd) [4/23] <no 8080>
SRA (IX+dd) $DD $CB $2E dd
SRA (IY+dd) $FD $CB $2E dd
Perform an arithmetic shift right on the byte pointed to by the index register plus the displacement. Bit zero moves to carry and bit 7 is duplicated into bit 6.
Bits affected: C, P, S, Z
Bits reset: H, N
--------------------------------------------------
SRA r [2/8] <no 8080>
SRA A $CB $2F
SRA B $CB $28
SRA C $CB $29
SRA D $CB $2A
SRA E $CB $2B
SRA H $CB $2C
SRA L $CB $2D
Perform an arithmetic shift right on register r. Bit zero moves to carry and bit 7 is duplicated into bit 6. The operation effectively halves the register value. The carry flag represents the remainder. The carry flag is set if the original number was odd.
Bits affected: C, P, S, Z
Bits reset: H, N
--------------------------------------------------
The following SRL instructions shift bits to the right.
!---!---!---!---!---!---!---!---! !---!
0 -> ! -> -> -> -> -> -> -> ->-----> ! !
!---!---!---!---!---!---!---!---! !---!
register carry
--------------------------------------------------
SRL (HL) [2/15] <no 8080>
SRL (HL) $CB $3E
Perform a logical shift right on the byte pointed to by the HL register pair. A zero bit is moved into bit 7. Bit zero moves to the carry flag.
Bits affected: C, P, Z
Bits reset: H, N, S
--------------------------------------------------
SRL (IX+dd) [4/23] <no 8080>
SRL (IY+dd) [4/23] <no 8080>
SRL (IX+dd) $DD $CB $3E dd
SRL (IY+dd) $FD $CB $3E dd
Perform a logical shift right on the byte pointed to by the index register plus the displacement. A zero bit is moved into bit 7. Bit zero moves to the carry flag.
Bits affected: C, P, Z
Bits reset: H, N, S
--------------------------------------------------
SRL r [2/8] <no 8080>
SRL A $CB $3F
SRL B $CB $38
SRL C $CB $39
SRL D $CB $3A
SRL E $CB $3B
SRL H $CB $3C
SRL L $CB $3D
Perform a logical shift right on register r. A zero bit is moved into bit 7. Bit zero moves to the carry flag.
Bits affected: C, P, S, Z
Bits reset: H, N
--------------------------------------------------
SUB (HL) [1/7] <SUB M> [1/7]
SUB (HL) $96 <SUB M>
Subtract the memory byte referenced by the HL pair from the accumulator. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SUB (IX+dd) [3/19] <no 8080>
SUB (IY+dd) [3/19] <no 8080>
SUB (IX+dd) $DD $96 dd
SUB (IY+dd) $FD $96 dd
Subtract the memory byte referenced by the index register plus the displacement from the value in the accumulator. The result is placed in A.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SUB r [1/4] <SUB r> [1/4]
SUB A $97 <SUB A>
SUB B $90 <SUB B>
SUB C $91 <SUB C>
SUB D $92 <SUB D>
SUB E $93 <SUB E>
SUB H $94 <SUB H>
SUB L $95 <SUB L>
Subtract the specified CPU register from the accumulator. The result is placed in the accumulator. Notice that Z-80 SUB mnemonic has only one operand, whereas there are two operands in the corresponding 8-bit ADC, ADD, and SBC mnemonics. The destination operand for all four of these instructions is always the accumulator. Consequently, the first operand is optional with some assemblers.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
SUB nn [2/7] <SUI nn> [2/7]
SUB nn $D6 nn <SUI nn>
Subtract the immediate byte nn from the accumulator. The result is placed in the accumulator.
Flags affected: C, H, O, S, Z
Flag set: N
--------------------------------------------------
XOR (HL) [1/7] <XRA M> [1/7]
XOR (HL) $AE <XRA M>
Perform a logical exclusive OR with the accumulator and the byte referenced by the HL pair. The result is placed in the accumulator.
Flags affected: P, S, Z
Flags reset: C, H, N
--------------------------------------------------
XOR (IX+dd) [3/19] <no 8080>
XOR (IY+dd) [3/19] <no 8080>
XOR (IX+dd) $DD $AE dd
XOR (IY+dd) $FD $AE dd
Perform a logical exclusive OR with the accumulator and the byte referenced by the sum of specified index register and the displacement. The result is placed in the accumulator.
Flags affected: P, S, Z
Flags reset: C, H, N
--------------------------------------------------
XOR r [1/4] <XRA r> [1/4]
XOR A $AF <XRA A>
XOR B $A8 <XRA B>
XOR C $A9 <XRA C>
XOR D $AA <XRA D>
XOR E $AB <XRA E>
XOR H $AC <XRA H>
XOR L $AD <XRA L>
Perform a logical exclusive OR with the accumulator and register r. The result is placed in the accumulator. The XOR A instruction is an efficient way to zero the accumulator, although all the flags are then reset. XOR A is also used to reset the carry flag.
Flags affected: P, S, Z
Flags reset: C, H, N
--------------------------------------------------
XOR nn [2/7] <XRI nn> [2/7]
XOR nn $EE nn <XRI nn>
Perform a logical exclusive OR with the accumulator and the byte nn. The result is placed in the accumulator.
Flags affected: P, S, Z
Flags reset: C, H, N